The invention relates to a trench capacitor and a corresponding fabrication method.
Integrated circuits (ICs) or chips, such as dynamic random access memory chips (DRAM), contain capacitors for storing a charge. In this case, the charge state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells which are provided in the form of rows and columns and are addressed by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is performed by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions isolated by a channel which is controlled by a gate. Depending on the direction of current flow, one diffusion region is referred to as the drain region and the other as the source region. One of the diffusion regions is connected to a bit line, the other diffusion region is connected to the capacitor and the gate is connected to a word line. By the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the diffusion regions through the channel is switched on and off.
The charge stored in the capacitor decreases over time on account of leakage currents. Before the charge has decreased to an indeterminable level below a threshold value, the storage capacitor must be refreshed. For this reason, these memory cells are referred to as dynamic RAM (DRAM).
U.S. Pat. No. 5,867,420 discloses trench capacitor formed in a substrate. The central problem in known types of DRAM is the production of a sufficiently large capacitance for the trench capacitor. This problem will be aggravated in the future by the advancing miniaturization of semiconductor components. The continuous increase in the integration density means that the area available per memory cell and thus the capacitance of the trench capacitor decrease ever further. An excessively low capacitance of the trench capacitor can adversely influence the functionality and usability of the memory device, since an excessively small quantity of charge is stored on it.
By way of example, sense amplifiers require a sufficient signal level for reliably reading out the information situated in the memory cells. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is too low, the ratio may be too small for generating an adequate signal.
A lower storage capacitance likewise requires a higher refresh frequency, because the quantity of charge stored in the trench capacitor is limited by its capacitance and additionally decreases due to leakage currents. If the quantity of charge falls below a minimum quantity of charge in the storage capacitor, then it is no longer possible for the information stored therein to be read out by the connected sense amplifiers, the information is lost and read errors arise.
One way of avoiding read errors is to reduce the leakage currents. Firstly, the leakage current can be reduced by a transistor; secondly, the leakage current can be reduced by a capacitor dielectric; and, finally, the leakage current can be reduced by a buried strap or a buried contact to a buried plate. An undesirably reduced retention time can be lengthened by these measures.
A trench capacitor is usually used in DRAMs. A trench capacitor has a three-dimensional structure which is formed in a silicon substrate. An increase in the volume and thus in the capacitance of the trench capacitor can be achieved by etching more deeply into the substrate. In this case, the increase in the capacitance of the trench capacitor does not cause the surface occupied by the memory cell to be enlarged. However, this method is also limited, since the attainable etching depth of the trench capacitor depends on the trench diameter, so that it is only possible to attain specific, finite aspect ratios.
As the increase in the integration density advances, the substrate surface available per memory cell decreases ever further. The associated reduction in the trench diameter inevitably leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is dimensioned from the outset to be so low that the charge which can be stored is insufficient for entirely satisfactory readout by the sense amplifiers connected downstream, then this results in read errors.
It is accordingly an object of the invention to provide a trench capacitor which overcomes the above-mentioned disadvantages of the heretofore-known trench capacitors of this general type and which has an increased capacitance for the same trench diameter and the same trench depth. A further object of the invention is to provide a method of fabricating such a trench capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a trench capacitor, including:
a substrate formed with a trench having a trench wall, the trench having an upper region and a lower region;
an insulation collar formed in the upper region of the trench wall;
a buried layer, the lower region of the trench at least partially extending through the buried layer;
a dielectric layer disposed at the trench wall in the lower region of the trench and at the insulation collar;
a conductive trench filling provided in the trench and serving as an inner capacitor electrode;
a conductive layer serving as an outer capacitor electrode, the conductive layer being disposed such that, in the lower region of the trench, the conductive layer is disposed between the substrate and the dielectric layer and, at the insulation collar, the conductive layer is disposed between the insulation collar and the dielectric layer; and
the conductive layer including a metal, a metal silicide or a metal nitride.
The idea underlying the present invention is using a conductive layer as an outer capacitor electrode. In conventional trench capacitors, the capacitor area is restricted to a lower region of a trench which lies below an insulation collar. By using the conductive layer in the lower region of the trench and on the insulation collar, the available area and thus the available capacitance is increased.
In one advantageous embodiment of the invention, a buried plate is formed in the substrate around the lower region of the trench, thereby improving the electrical contact between a buried well and the conductive layer.
In a further advantageous embodiment of the invention, the trench capacitor is doped below the surface of the substrate in the region of a buried strap, so that a buried contact is produced and advantageously electrically connects the buried strap or a trench filling to a source region of a transistor. The doping in the region of the buried contact may be introduced for example by implantation, plasma doping and/or gas phase doping or another suitable method.
In a further advantageous embodiment of the invention, the conductive buried strap is formed on the conductive trench filling, which forms the inner capacitor electrode. The advantage of this procedure resides in the greater flexibility in the production of the buried contact.
A further advantageous embodiment of the trench capacitor according to the invention provides the formation of an insulation web for insulating an upper region of the conductive layer. The insulation web has the task of preventing a charge transport from the conductive layer to the electrically interconnected conductive trench filling, the conductive buried strap and the buried contact. As a result, the retention time of the memory cell is advantageously lengthened and undesirable bit errors on account of leakage currents are prevented. In a specific embodiment, the insulation web is composed of an oxide, nitride or oxynitride.
A further advantageous embodiment of the invention provides for the conductive layer to be composed of silicon (doped or undoped), polycrystalline or amorphous), of a metal, of a silicide or a nitride. In this case, the metal used may be titanium, tungsten, molybdenum or cobalt. The silicide used may be titanium silicide, tungsten silicide, molybdenum silicide or cobalt silicide and the nitride used may be titanium nitride or tungsten nitride.
According to another feature of the invention, a conductive buried strap is disposed on the conductive trench filling.
According to another feature of the invention, the insulation web is configured to prevent a charge transport from the conductive layer to the conductive trench filling.
According to yet another feature of the invention, a conductive buried strap is disposed on the conductive trench filling; and an insulation web lines the conductive layer at least in an upper region thereof, the insulation web is configured to prevent a charge transport from the conductive layer to the conductive buried strap.
According to a further feature of the invention, an insulation web lines the conductive layer at least in an upper region thereof. The insulation web prevents a charge transport from the conductive layer to a buried contact.
With the objects of the invention in view there is also provided, a method for fabricating a trench capacitor, the method includes the steps of:
introducing a buried layer into a substrate;
forming a trench with an upper region and a lower region in the substrate;
forming an insulation collar in the upper region on a trench wall of the trench;
forming an outer capacitor electrode by lining the lower region of the trench and the insulation collar with a conductive layer;
forming a dielectric layer on the conductive layer at the lower region of the trench and at the insulation collar;
filling the trench with a conductive trench filling serving as an inner capacitor electrode; removing the conductive trench filling, the conductive layer and the dielectric layer as far as a level at which the insulation collar is disposed;
conformally depositing an insulation layer;
removing the insulation layer above the conductive trench filling; and
removing the insulation layer such that the substrate is uncovered in the upper region of the trench.
According to another mode of the invention, a buried plate is formed in the substrate adjacent to the lower region of the trench prior to forming the conductive layer such that the buried plate makes contact with the buried layer which forms a buried well.
According to yet another mode of the invention, a conductive buried strap is formed on the conductive trench filling such that the conductive buried strap electrically contacts a buried contact.
According to another mode of the invention, the conductive trench filling, the dielectric layer and the conductive layer are removed to a point below an upper end of the insulation collar.
According to a further mode of the invention, the conductive trench filling, the dielectric layer and the conductive layer are removed only as far as an upper end of the insulation collar.
An advantageous mode of the method according to the invention forms, after forming the insulation collar, a buried plate in the substrate, in the vicinity of the lower region of the trench, so that the buried plate makes contact with a buried well.
A further advantageous mode of the method according to the invention forms an insulation web in the upper region of the insulation collar. The insulation web prevents leakage currents which could discharge the trench capacitor.
In a further method variant, introducing dopant in order to form the buried contact advantageously reduces the contact resistance of the trench capacitor.
According to another mode of the invention, the fabrication method additionally forms a conductive buried strap in the trench. The formation of the buried strap increases the process flexibility since the dopant for fabricating the buried contact can be introduced after the etching-back of the trench filling from within the trench through a vertical interface. Afterward, the conductive strap is formed in order to produce the electrical connection.
The trench capacitor according to the invention and the fabrication method according to the invention have the advantage over conventional methods that the capacitance of the trench capacitor is increased. In particular, the failures due to charges that are too small are reduced and, at the same time, the process yield is increased.
A further advantage is the possibility of reducing the diameter of the trench in the context of advancing miniaturization, since the trench capacitor according to the invention and the fabrication method according to the invention compensate for the reduction in capacitance which stems from the reduction of the area available per memory cell.
The conductive layer may be deposited by CVD (Chemical Vapor Deposition), PECVD (Plasma-Enhanced Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition) methods. In this case, it is possible to use materials such as doped or undoped, polycrystalline or amorphous silicon. The doping may be introduced either during the deposition or into the already deposited layer. The doping may be carried out by implantation, gas phase doping and/or plasma-enhanced doping. Furthermore, the conductive layer may be fabricated from a metal in the methods mentioned above. Suitable metals are titanium or tungsten, for example.
With the methods mentioned above it is also possible to deposit silicides such as, for example, tungsten silicide, titanium silicide, molybdenum silicide or cobalt silicide. In order to form a silicide, the metal and the silicon may be deposited in separate steps and then be siliconized at a temperature suitable for the system of materials. Suitable temperatures for this lie between 600xc2x0 C. and 1100xc2x0 C.
It is also possible to use a nitride, such as titanium nitride or tungsten nitride, for example. On the one hand, the nitride may be deposited directly by the known methods in order to form the conductive layer. On the other hand, it is also possible for the deposited layer to be subsequently nitrided, with suitable temperatures and process gases.
A further advantage of the conductive layer according to the invention is its effect as an adhesion layer and barrier layer for the storage dielectric used.
The methods mentioned in the previous sections, for fabricating the conductive layer, can also be used for forming the conductive trench filling.
All materials which are sufficiently thermostable and conductive can be used for forming the conductive layer and for forming the conductive trench filling.
In addition, the deposited buried plate is insulated from the conductive trench filling, from the conductive buried strap and from the buried contact by an insulation web in the region of the buried strap. The buried insulation web is composed of insulating material, such as oxide, nitride or oxynitride, for example.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a trench capacitor with capacitor electrodes and a corresponding fabrication method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.